Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization

ABSTRACT

A method for the post-etch cleaning of multi-level, damascene structures which minimizes, or substantially prevents, localized corrosion of underlying copper metallization comprises subjecting an intermediate structure in the fabrication of a multi-level, damascene structure, which structure includes an underlying copper metallization layer and an opening etched therein which exposes at least a portion of the underlying copper metallization layer, to an aqueous or acidic wash solution, in an environment substantially shielded from ambient light, to substantially remove any post-etch residues which may be present on the structure. In one embodiment, the aqueous or acidic wash solution has a nonzero static etch rate when applied to both the copper and conventional dielectric materials, e.g., silicon dioxide.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 10/665,238,filed Sep. 17, 2003, pending.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devicefabrication. More particularly, the present invention relates to apost-etch cleaning method for multi-level, damascene structures whichminimizes, or substantially prevents, localized corrosion of underlyingcopper metallization.

BACKGROUND OF THE INVENTION

Integration of ever increasing numbers of active elements on highdensity integrated circuits (ICs) has necessitated that such ICs featuremultiple layers of metal interconnects. In the multi-level metallizationarchitecture used in today's semiconductor devices, aluminummetallization is generally used, as it offers a number of advantageswith regard to, for instance, ease of fabrication. However, using stateof the art 0.18 μm technology, opening dimensions of 0.25 μm are beingreached and interconnects are becoming a limiting factor in terms of thecircuit speed of such high performance ICs. This is due, in part, to theresistivity of the interconnects.

One solution for lowering the resistance of interconnects which has beenexplored in the industry is to change the interconnect metallizationfrom aluminum to copper. Copper has better conductivity (ρ=1.7 Ω·cm)than aluminum (ρ=2.7 Ω·cm) and has good resistance to electromigration.However, the use of copper for interconnect metallization presents anumber of problems. For instance, in conventional aluminum metallizationprocesses, a subtractive plasma etch process is generally utilized toform the metal interconnects. The plasma etch process typicallycomprises depositing an aluminum layer on a desired substrate, applyinga patterned hard mask or photoresist over the aluminum layer, patternetching the aluminum layer using wet or dry etch techniques, anddepositing a dielectric material over the surface of the patternedaluminum layer to provide isolation of the conductive lines and contactswhich comprise the IC.

Due to the chemical and physical properties thereof, subtractive plasmaetching of copper is more difficult than subtractive plasma etching ofaluminum. More particularly, although copper, like aluminum, reacts atlow temperatures with the chlorine typically present in plasma etchgases, the product of the reaction is not as volatile as the reactionproduct with aluminum. This causes copper to corrode, rather than etch,when subjected to conditions similar to those used to etch aluminum. Assuch, the conventional substractive plasma etch technique used to formaluminum metallization is not adequate for forming copper metallization.

One processing solution which has emerged in the semiconductor industryto introduce copper metallization is a damascene process in which adesired metallization pattern is etched into a dielectric layer,backfilled with a desired metal and subsequently planarized using, forinstance, an abrasive planarization technique such as chemicalmechanical planarization (CMP). Single damascene processes are used toform only wiring lines or via interconnects in a single dielectriclayer. Dual damascene processes, however, may be used to incorporateboth inlaid metal lines and via interconnects in a single dielectriclayer. Dual damascene processes are generally utilized as, in additionto permitting the effective introduction of copper metallization, theprocesses provide potentially significant reductions in processing cost.

The dual damascene technique relies upon electroplating metal intopreformed vias and trenches, followed by planarizing to remove excessmetal from the wafer surface. While either the trench or the via may beetched first in the formation of dual damascene structures, mostsemiconductor manufacturers have chosen to adopt the via-first approach.The major drawback of the trench-first approach is that after the trenchhas been etched, the photoresist that is applied for the via etch willcompletely fill the trench creating local regions of extra thick resistin the areas where the vias are to be patterned. Forming the very finevia structures in such thick resist is extremely difficult and, as aresult, the trench-first approach to dual damascene formation has beenlargely abandoned.

Referring to FIGS. 1A through 1K, an exemplary, via-first, dualdamascene process sequence is illustrated. It will be understood bythose of ordinary skill in the art that the methods and structuresdescribed herein do not form a complete process for manufacturingmulti-level ICs. The remainder of the process is known to those ofordinary skill in the art and, therefore, only the process steps andstructures necessary to understand the conventional, via-first, dualdamascene process sequence are described herein.

Referring to FIG. 1A, a cross-sectional view of a first intermediatestructure 10 in the fabrication of a multi-level, dual damascenestructure 34 (see, FIG. 1K) comprising an underlying coppermetallization layer 12 (e.g., a copper line or grounded copper contact)is illustrated. The first intermediate structure 10 includes a barrierlayer 14 which resides on the underlying copper metallization layer 12.It will be understood by those of ordinary skill in the art that thefigures presented in conjunction with this description are not meant tobe actual cross-sectional views of any particular portion of an actualmulti-level, dual damascene structure, but are merely idealizedrepresentations which are employed to more clearly and fully depict theconventional via-first, dual damascene process sequence than wouldotherwise be possible. Elements common between the figures maintain thesame numeric designation.

Over the barrier layer 14, a first interlevel dielectric layer 16, e.g.,a silicon dioxide layer, may be formed. In multi-level metallization,the damascene process sequence may be used to incorporate coppermetallization at all levels in which such metallization is desired. Inthose cases in which an upper level of metallization is to beincorporated, i.e., where there is already an underlying coppermetallization layer 12 as illustrated in FIGS. 1A-1K, the barrier layer14 is necessary because the copper in the underlying metallization layer12 can easily diffuse into the first interlevel dielectric layer 16 andexhibits poor adhesion thereto. The barrier layer 14 may also be used asan etch stop when the first interlevel dielectric layer 16 is etched, asmore fully described below. In this regard, the etch rate of thematerial of the barrier layer 14 should be significantly lower than thatof the material of the first interlevel dielectric layer 16 in order toensure adequate etch selectivity. The difference in etch rate betweensilicon dioxide (an exemplary material for the first interleveldielectric layer 16) and silicon nitride (an exemplary material for thebarrier layer 14) adequately provides such selectivity.

An embedded etch stop layer 18 formed of, for instance, silicon nitride,may be disposed over the first interlevel dielectric layer 16, and asecond interlevel dielectric layer 20 may be formed over the embeddedetch stop layer 18, as shown.

Referring to FIG. 1B, a via photoresist layer 22 may be formed over thesecond interlevel dielectric layer 20 and photolithographicallypatterned. Subsequently, as shown in FIG. 1C, an etch, typically ananisotropic dry etch, may be performed extending the via pattern throughthe second interlevel dielectric layer 20, the embedded etch stop layer18 and the first interlevel dielectric layer 16, stopping at the barrierlayer 14. This etch forms a via 23. It will be understood by those ofordinary skill in the art that multiple etch steps may be required toetch through each of the desired layers. If the via etch is not stoppedat the barrier layer 14, copper from the underlying copper metallizationlayer 12 will sputter into the unprotected via 23. The copper will thenquickly diffuse into the interlevel dielectric layers 16 and 20, whichmay lead to device failure.

Next, the via photoresist layer 22 may be removed (e.g., using a plasmastrip technique), as shown in FIG. 1D. The via 23 may subsequently becleaned to remove any residual photoresist material and any dielectricetch material residues therefrom. In addition to preventing diffusioninto, and enhancing adhesion to, the first interlevel dielectric layer16, the barrier layer 14 also permits the via etch residues to beisolated from the underlying copper metallization layer 12, allowing thevia 23 to be cleaned at this stage according to conventional techniques.

Next, as shown in FIG. 1E, a trench photoresist layer 24 may be formedover the second interlevel dielectric layer 20 and photolithographicallypatterned. Some of the trench photoresist layer 24 will be deposited inthe bottom of the via 23 and will prevent the lower portion of the via23 from being overetched during the trench etch process. Those ofordinary skill in the art will understand that an organic antireflectivecoating (ARC) or the like (not shown) may also be used to protect thevia 23 and the portion of the barrier layer 14 underlying the via 23, ifdesired.

Subsequently, as shown in FIG. 1F, an etch, typically an anisotropic dryetch, may be performed to extend the trench pattern through the secondinterlevel dielectric layer 20, the etch stopping at the embedded etchstop layer 18. This etch forms a trench 25. It will be understood bythose of ordinary skill in the art that, if desired, the intermediatestructure 10 may have only a single interlevel dielectric layer and bevoid of the embedded etch stop layer 18 altogether. However, if anembedded etch stop layer 18 is not used, the etch system must be capableof a very uniform etch to ensure all trenches 25 are of the same depthacross the wafer, and from wafer to wafer. This could be difficult sincethere is no real endpoint indicator and the depth of the trench 25 canonly be determined by the length of time of the etch. The trenchphotoresist layer 24 may subsequently be stripped (e.g., using a plasmastrip technique), as shown in FIG. 1G.

In order to adequately connect the upper metallization level to theunderlying copper metallization layer 12, the barrier layer 14 must be“punched-through” at the bottom of the via 23, once the via 23 and thetrench 25 have been etched, as previously described. This step is shownin FIG. 1H and is typically accomplished using a separate etch selectivefor the material of the barrier layer 14.

Once the barrier layer 14 has been punched-through beneath the via 23,the dual damascene structure 34 may be completed by forming a thindiffusion barrier 26 lining the bottom and sidewalls 23 a and 25 a ofthe via 23 and the trench 25, respectively, optionally forming a copper“seed” layer 28 over the diffusion barrier 26, depositing bulk copper 30over the structure such that the trench 25 and via 23 are filledtherewith (see, FIG. 1I) and planarizing the bulk copper 30 to stop onthe surface of the second interlevel dielectric layer 20 using, e.g.,CMP (see, FIG. 1J). The dual damascene structure 34 may subsequently becompleted by deposition of a thin cap layer 32 (e.g., a silicon nitridecap layer) over the planarized bulk copper 30 and the second interleveldielectric layer 20.

When the barrier layer 14 is etched (see, FIG. 1H), back-sputtering ofcopper onto the sidewalls 23 a and 25 a of the via 23 and the trench 25,respectively, or elsewhere on the structure, may occur. Additionally,post-etch residues from etching the dielectric layers 16 and 20 and theembedded etch stop layer 18 may remain as well. It is desirable toremove this contamination prior to completion of the metallization,i.e., prior to deposition of the diffusion barrier 26. If not removed,the residues will remain trapped under the diffusion barrier 26.Residues, particularly copper residues, located on the wrong side of thediffusion barrier 26 may contribute to or cause device failure if, forinstance, they diffuse into the dielectric layers 16 and 20.

Conventional post-etch cleaning of metallization structures generallyinvolves the use of an aqueous or acidic wash solution using, e.g., adilute hydrofluoric acid (HF) solution. However, the use of coppermetallization creates problems with such aqueous wash techniques as theexposed copper at the bottom of the etched vias is more susceptible tolocalized corrosion than previously used metals, such as aluminum.Corrosion, which may be facilitated by aqueous and/or acidic washtechniques, can lead to pitting and opens in the metallization, whichcan adversely affect the electrical properties of the semiconductordevice. As a result, many semiconductor device manufacturers use asolvent or nonaqueous wash to remove post-etch residues prior tocompletion of dual damascene structures. Solvent/nonaqueous washes,however, produce waste which necessitates relatively expensive disposaltechniques.

Corrosion of copper (i.e., the electrochemical dissolution thereof) insemiconductor devices has been found to be a photo-induced phenomenoncaused by exposure of the PN junctions on the wafer to light. Thisphotovoltaic effect is known to those of ordinary skill in the art andhas been described in some detail in U.S. Pat. No. 6,251,787 toEdelstein et al. (hereinafter the “Edelstein et al. patent”), which ishereby incorporated by reference herein as if set forth in its entirety.In the Edelstein et al. patent, corrosion of a copper layer subsequentto chemical mechanical polishing thereof is addressed.

Accordingly, the inventor hereof has recognized that a post-etchcleaning method for multi-level, damascene structures which minimizes,or substantially prevents, localized corrosion of underlying coppermetallization, yet permits the use of aqueous or acidic wash solutionswould be advantageous.

BRIEF SUMMARY OF THE INVENTION

The present invention, in one exemplary embodiment, includes a methodfor post-etch cleaning of a damascene structures, which methodminimizes, or substantially prevents, localized corrosion of underlyingcopper metallization. The method comprises subjecting at least a portionof a copper metallization layer to an aqueous or acidic wash solution inan environment substantially shielded from ambient light. The aqueous oracidic wash solution substantially removes any post-etch residues thatmay be present on sidewalls of an opening through which the coppermetallization layer is exposed. In one embodiment, the aqueous or acidicwash solution has a nonzero static etch rate when applied to both copperand conventional dielectric materials, e.g., silicon dioxide. Anexemplary wash solution comprises about 7.0% by weight acetic acid,about 0.4% by weight nitric acid and about 0.15% by weight hydrofluoricacid. If this exemplary wash solution is utilized, the intermediatestructure may be exposed to the solution for a period of time rangingfrom about thirty seconds to about two minutes, depending upon theamount of residue to be removed therefrom.

Other features and advantages of the present invention will becomeapparent to those of ordinary skill in the art through consideration ofthe ensuing description, the accompanying drawings, and the appendedclaims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention may be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIGS. 1A through 1K are side cross-sectional views illustrating aconventional method for forming a multi-level, dual damascene structurewith which the post-etch cleaning method of the present invention may beutilized.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to a method for the post-etch cleaningof multi-level damascene structures having underlying coppermetallization. The method provides a way in which localized,photo-induced corrosion of copper metallization underlying etchedopenings in damascene structures may be minimized, or substantiallyprevented, while permitting the use of aqueous or acidic wash solutionsto clean the structures. The particular embodiments described herein areintended in all respects to be illustrative rather than restrictive.Other and further embodiments will become apparent to those of ordinaryskill in the art to which the invention pertains without departing fromits scope.

The method of the present invention comprises subjecting an intermediatestructure in the formation of a multi-level damascene structure, whichintermediate structure includes an etched opening therein through whichat least a portion of an underlying copper metallization layer isexposed, to an aqueous or acidic wash solution, in an environmentsubstantially shielded from ambient light, to remove any residues whichmay be present on the sidewalls of the etched opening, or elsewhere onthe intermediate structure. One example of such an intermediatestructure is the intermediate structure 36 shown in FIG. 1H.

As previously described, the intermediate structure 36 shown in FIG. 1His at a stage of multi-level, dual damascene structure processingwherein the barrier layer 14, which had been separating the underlyingcopper metallization layer 12 from the first interlevel dielectric layer16 and the unprotected via 23, has been punched-through, exposing atleast a portion of the underlying copper metallization layer 12. If theintermediate structure 36 were to be cleaned utilizing conventionalaqueous wash techniques, while subjecting the exposed portion of thecopper metallization layer 12 to ambient light, dissolution of thecopper comprising the copper metallization layer 12 would be likely tooccur. This is because not only does the ambient light causephoto-induced corrosion, as previously described, it has been observedthat use of aqueous or acidic wash solutions (i.e., solutions having ahigh ionic content) in the presence of ambient light actuallyfacilitates such corrosion beyond that which may be observed by exposureto ambient light alone. If, however, the intermediate structure 36 iscleaned utilizing the post-etch cleaning method of the presentinvention, localized corrosion of the exposed portion of the underlyingcopper metallization layer 12 may be substantially prevented.

It is currently preferred that an aqueous/acidic wash solutioncomprising about 7.0% by weight acetic acid, about 0.4% by weight nitricacid and about 0.15% by weight hydrofluoric acid be utilized, incombination with reduced ambient light conditions, to remove any copperresidues, interlevel dielectric material residues, or other residuesthat are likely to be present on the sidewalls 23 a and 25 arespectively, of the via 23 or trench 25, or elsewhere on theintermediate structure 36. This acetic/nitric/hydrofluoric acid solutionhas a static etch rate of about 15 Å/minute for both metals, includingcopper, and conventional dielectric materials, including silicondioxide. Thus, this solution permits a uniform etch of substantially allof the residues that are likely to be present on the sidewalls 23 a and25 a, respectively, of the via 23 or trench 25, or elsewhere on theintermediate structure 36. The intermediate structure 36 may be exposedto the aqueous wash solution, in an environment substantially shieldedfrom ambient light, for a period of time ranging from about thirtyseconds to about two minutes, the duration depending upon the amount ofresidue to be removed from the intermediate structure 36.

The method of the present invention may also be utilized with otheraqueous or acidic wash solutions known to those of ordinary skill in theart including, but not limited to, diluted hydrofluoric acid (HF). It iscurrently preferred that the aqueous or acidic wash solution utilizedhave a nonzero static etch rate for both copper and conventionaldielectric materials. The duration of exposure to the solution, inreduced ambient light conditions, will be dependent upon the static etchrate and the amount of residue present on the post-etch structure.

In practice, the structure to be cleaned, which structure typicallywould include a plurality of vias and trenches etched therein, would beplaced in a reduced ambient light chamber which preferably completelyshields and isolates the structure from all ambient light and theaqueous/acidic wash solution would be applied to the etched surfacesthereof for a period of time (in the case of theacetic/nitric/hydrofluoric acid wash solution discussed above) rangingfrom about thirty seconds to about two minutes. Again, the duration ofexposure to the wash solution would depend upon the amount of residue tobe removed from the structure. The structure would subsequently beremoved from the chamber and a diffusion barrier 26 formed thereover, aspreviously discussed, followed by an optional seed layer 28 and a bulkcopper layer 30. It is currently preferred that the structure remain inreduced ambient light conditions until the diffusion barrier 26 isformed over the exposed portion of the underlying copper metallizationlayer 12 to further minimize photo-induced corrosion thereof.

The method of the present invention is not limited to copper upper-levelmetallization but may be utilized for upper-level metallization formedof any metal known in the art. That is, the method hereof provides a wayin which underlying copper metallization (e.g., grounded coppercontacts) may be substantially protected from localized corrosion.However, if, for example, an aluminum or tungsten metallization layer isdesired overlaying a copper metallization layer, the method of thepresent invention may still be utilized to minimize or substantiallyprevent corrosion of the underlying copper metallization, provided thealuminum or tungsten metallization layer is formed using a damasceneprocess. It will be further understood that while FIGS. 1A through 1Killustrate formation of a dual damascene structure formed over anunderlying copper metallization layer, the method of the presentinvention may also be utilized if a single damascene structure isformed. In fact, in any situation wherein copper is exposed through anopening etched in a material layer formed thereover, the process of thepresent invention may be utilized.

The present invention has been described in relation to particularembodiments that are intended in all respects to be illustrative ratherthan restrictive. It is to be understood that the invention defined bythe appended claims is not to be limited by particular details set forthin the above description and that alternative embodiments will becomeapparent to those of ordinary skill in the art to which the presentinvention pertains without departing from the spirit and scope thereof.

1. A method for post-etch cleaning of a damascene structure having abarrier layer disposed over at least a portion of a copper metallizationlayer and a dielectric layer disposed over at least a portion of thebarrier layer, comprising: etching at least one opening through adielectric layer and a barrier layer to expose at least a portion of acopper metallization layer and to form an etched structure; andsubjecting the etched structure to an aqueous solution in an environmentwherein the etched structure is substantially shielded from ambientlight, wherein the aqueous solution comprises hydrofluoric acid.
 2. Themethod of claim 1, wherein subjecting the etched structure to an aqueoussolution in an environment wherein the etched structure is substantiallyshielded from ambient light comprises removing residues from sidewallsof the at least one opening.
 3. The method of claim 1, whereinsubjecting the etched structure to an aqueous solution in an environmentwherein the etched structure is substantially shielded from ambientlight comprises removing copper residues or dielectric material residuesfrom sidewalls of the at least one opening.
 4. The method of claim 1,wherein subjecting the etched structure to an aqueous solution in anenvironment wherein the etched structure is substantially shielded fromambient light comprises removing copper residues or dielectric materialresidues from sidewalls of the at least one opening at a static etchrate of about 15 Å/minute.
 5. The method of claim 1, wherein subjectingthe etched structure to an aqueous solution in an environment whereinthe etched structure is substantially shielded from ambient lightcomprises subjecting the etched structure to the aqueous solution for aperiod of time ranging from about 30 seconds to about 2 minutes.
 6. Themethod of claim 1, further comprising forming a diffusion barrier overthe etched structure subsequent to subjecting the etched structure tothe aqueous solution while maintaining the etched structure in theenvironment wherein the etched structure is substantially shielded fromambient light.
 7. The method of claim 6, further comprising: forming abulk copper layer over the diffusion barrier such that the at least oneopening is filled therewith; and planarizing the bulk copper layer to asurface of the dielectric layer.
 8. A method of post-etch cleaning of adamascene structure, comprising: subjecting at least a portion of acopper metallization layer to an aqueous solution in an environmentwherein the at least a portion of the copper metallization layer issubstantially shielded from ambient light, wherein the aqueous solutioncomprises hydrofluoric acid.
 9. The method of claim 8, whereinsubjecting at least a portion of a copper metallization layer to anaqueous solution in an environment wherein the at least a portion of thecopper metallization layer is substantially shielded from ambient lightcomprises subjecting the at least a portion of the copper metallizationlayer to an aqueous solution that comprises about 7.0% by weight ofacetic acid, about 0.4% by weight of nitric acid, and about 0.15% byweight of hydrofluoric acid.
 10. The method of claim 8, whereinsubjecting at least a portion of a copper metallization layer to anaqueous solution in an environment wherein the at least a portion of thecopper metallization layer is substantially shielded from ambient lightcomprises removing residues from sidewalls of at least one openingthrough which the at least a portion of the copper metallization layeris exposed.
 11. The method of claim 8, wherein subjecting at least aportion of a copper metallization layer to an aqueous solution in anenvironment wherein the at least a portion of the copper metallizationlayer is substantially shielded from ambient light comprises removingcopper residues or dielectric material residues from sidewalls of atleast one opening through which the at least a portion of the coppermetallization layer is exposed.
 12. The method of claim 8, whereinsubjecting at least a portion of a copper metallization layer to anaqueous solution in an environment wherein the at least a portion of thecopper metallization layer is substantially shielded from ambient lightcomprises removing copper residues or dielectric material residues at astatic etch rate of about 15 Å/minute from sidewalls of at least oneopening through which the at least a portion of the copper metallizationlayer is exposed.
 13. The method of claim 8, wherein subjecting at leasta portion of a copper metallization layer to an aqueous solution in anenvironment wherein the at least a portion of the copper metallizationlayer is substantially shielded from ambient light comprises subjectingthe at least a portion of the copper metallization layer to the aqueoussolution for a period of time ranging from about 30 seconds to about 2minutes.